The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a system and method that facilitates debugging of internal component scan test faults.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results comprise a variety of components or devices including microelectronic integrated circuits. Usually the components or devices of an electronic system are required to operate properly in order for the desired results to be realized. An efficient and reliable integrated circuit (IC) testing system and method is very important for assuring an IC operates properly.
The complexity of commonly used integrated circuits included in system-on-chip (SOC) designs has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modem BIST techniques typically include the insertion of a scan test architecture in an IC. Scan testing of complex electronic systems and circuits often includes the application of test vectors to stimulate certain aspects of a circuit (e.g., a functional logic component) and observation of the resulting output from the circuit. Usually, scan test architectures include scan test components or devices (e.g., scan test cells) coupled together to form a scan test chain. The scan test elements communicate test vectors to components of an IC and interact with functional logic utilized to perform non-test or normal operations of the IC. Typically, scan test chains are designed to scan or shift scan test information (e.g., test vectors) to appropriate locations in a circuit, capture scan test information and then shift the scan test information off the IC.
Usually it is desirable to have significant scan test coverage, typically the greater the test coverage the greater the capacity of a scan test system and method to detect faults. Boundary scan testing is a very common method of scan testing included in typical BIST schemes. International Electrical and Electronic Engineering (IEEE) Standard 1149.1 (also referred to as Joint Task Action Group (JTAG)) boundary scan compliant architecture is one of the most prevalent boundary scan schemes. It is also very important to have internal scan test capabilities to provide greater scan test coverage. Having both internal and boundary scan capability often requires significant commitment of limited IC resources, such as increased dedication of scarce IC pins to scan test operations.
Debugging scan test results often requires complicated analysis of logic values retrieved from appropriately selected circuit nodes (e.g., at the outputs or inputs of functional logic) after the application of test vectors. Traditional long scan test vectors provided by automated test pattern generation (ATPG) tools make scan test debugging very difficult. Test patterns provided by an ATPG tool often appear to an engineer as random data shifted onto the chip. Usually the engineers do not have an in-depth understanding of each scan test pattern generated by ATPG tools. Common methods of attempting to solve scan test debug difficulties include forcing certain predetermined patterns into a scan test input and attempting to infer what is causing the problem based upon how a scan test output behaves or changes. However, without a good understanding of the test vector pattern it is usually difficult to accurately identify a fault.
Scan test patterns are typically very long (scan test chain lengths of thousands of scan elements are common) and it is inherently difficult to debug failures or fault indications. Analyzing the behavior of limited number of circuit elements in response to a test vector is relatively easy and making an inference identifying the element causing a fault problem is relatively accurate. However, each element added to a scan test chain results in another element that is a potential source of a fault. Accurately inferring which element is the source of the fault becomes increasingly more difficult the greater the number of scan test elements since there are more possible sources of causing the problem.
Traditional methods of attempting to solve scan test debug difficulties usually consume significant resources and often lack a high degree of reliability. For example, utilizing small scan test chains with shorter test vectors typically results in significantly increasing the requirement for dedication of scarce pin resources to scan test operations. While small scan test chains may offer some advantages, they do not offer the flexibility of testing large sections of a system and make it difficult to test the operations of an entire system since only a small portion is tested at any given time. Thus, attempts to identify sources of faults in traditional scan test operations is often inaccurate and unreliable.
What is required is a system and method that facilitates simplified debugging of internal component scan test results. The system and method should support efficient scan testing of integrated circuit components and accommodate utilization of existing scan testing architectures with minimal adverse redesign impacts to existing IC designs.
The present invention is a system and method that facilitates simplified debugging of internal component scan test results. The test access port (TAP) controlled internal scan test intermediate debugging system and method of the present invention is capable of supporting efficient scan testing of integrated circuit components with an ATPG tool while assisting debugging operations. The present invention system and method accommodates utilization of existing scan testing architectures with minimal adverse redesign impacts to existing IC designs, normal operations and manufacturing processes. The present invention enhances internal scan test analysis of digital circuits and is compatible with traditional scan test methodologies.
One embodiment of a present invention TAP controlled internal scan test intermediate debugging system comprises a intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input port (e.g., a pin), a scan test chain final output port. The components of the TAP controlled internal scan test intermediate debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals via a TAP. The intermediate TAP controller internal scan test system controls transmission of an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system comprises an internal scan observe register, a TAP output control circuit and a TAP output multiplexer (MUX). The information stored in the scan observe register indicates which intermediate internal scan test chain signal to forward as a TDO signal. The design circuit blocks perform designated functions during normal operation mode of the IC. During scan test operations scan test elements of the design circuit blocks shift in scan test vectors, capture resulting scan test information and shift out the scan test results. The scan test chain primary input port provides a communication port for scan test input information and the scan test chain final output port (e.g., a pin) provides a communication port for scan test output information.
By selectively transmitting intermediate internal scan test chain signals (ISS) off of the IC, manipulation of a scan test vector value by a relatively small number of design circuit blocks is isolated in an analytical sense from manipulations by other design circuit blocks. If an intermediate ISS is an unexpected value it provides an indication that a fault may exist in one or more of a relatively small number of design circuit blocks. Isolating the fault to a limited number of design circuit blocks facilitates debugging without having to consider the manipulation of test vector values by other design circuit blocks. The present invention also conveniently facilitates testing of a relatively large scan test chain by providing scan test results on the scan test chain final output pin at the same time. Thus, the present invention facilitates simplified debugging of internal scan test results by isolating scan test vector inputs to a design circuit block and an intermediate scan test signal output of the design circuit block.